In the processes of chip manufacturing, the dimensions of the components constantly decrease, going from measurements of a few tens of nanometers, as in older specimens, to dimensions of less than 10 nanometers today in the most advanced chips. This ongoing race towards miniaturization is crucial to improve performance of chips, reduce energy consumption and increase the density of transistors in integrated circuits. While the nanometer is still the reference unit of measurement to express the size of the transistors or rather the average size of the gate of each transistor, Intel opened the angstrom era by presenting its 20Å and 18Å construction processes, equivalent to 2 and 1.8 nanometers respectively. It’s still all on paper because the first 20Å chips should arrive during 2024.
Although Intel’s new chips are set to hit the market before its own, the Taiwanese manufacturer TSMC claims today that its technology N3P (3 nanometers) will offer results comparable to those of the 18Å process while N2 (2 nm) it will be able to beat the Intel proposal across the board, therefore in terms of power, performance and area.
TSMC looks with great confidence to the future of its chips
In June 2023 we explained in detail what changes with the 2nm TSMC chips: we invite you to reread that article because it contains several interesting information on design techniques and creation of modern microchips.
During a meeting with investors, the CEO of TSMC – CC Wei – stated that the N2 technology, more advanced than both N3P and 18A, will be the most advanced ever in the semiconductor industry when it launches on the market in 2025.
The expression production node is widely used in the semiconductor industry and chip manufacturing to describe a specific generation of a manufacturing technology. Indicate the minimum dimensions of the structures that can be produced using that generation of technology.
What Intel is doing with the 20Å and 18Å manufacturing nodes
Intel’s 20Å manufacturing node, scheduled for 2024, promises to represent an innovative breakthrough as it will introduce the use of transistors RibbonFET gate-all-around and a rear-facing power distribution network (BSPDN). The name “Ribbon” comes from structure of the transistor which features a thin, flat channel, rather than a traditional sheet- or strip-shaped channel. The objective is to obtain improved performance compared to traditional transistors, thanks to the reduction of electrical resistance and the improvement of energy efficiency.
The expression gate-all-around refers to gate configuration, which is the electrode that controls the flow of current through the transistor channel. In a transistor gate-all-aroundthe gate completely surrounds the channel, allowing for greater control over the current and improving the overall performance of the transistor.
Furthermore, in the past, the back part of the silicon wafer was little used for electronic purposes. With the solution BSPDN the interconnections between power sources (such as voltage sources) and power-requiring chip components (for example, transistors) are located right on the back. Instead of just using the front surface of the wafer, the BSPDN scheme uses the back to improve power distribution.
According to Intel, this approach not only brings Moore’s law back to life but allows for higher performance, lower power consumption and greater transistor density. The 18Å production node will complete the new approach between the end of 2024 and the beginning of 2025.
How TSMC is moving
TSMC’s 3nm N3, N3E, N3P and N3X manufacturing processes all rely on proven FinFET transistors and traditional power networking. The largest semiconductor manufacturer appears to be in no rush to use GAAFET and BSPDN transistors. They will be used for the first time in the N2 production node expected for the second half of 2025.
For now, CC Wei underlines that N3P is comparable in terms of energy performance with Intel’s 18Å, although technologically more mature, already available and at significantly lower costs.
For its part, one of Intel’s main goals for the next few years is to beat TSMC in terms of technological leadership by getting the project off the ground Intel Foundry Services (IFS) 2.0 strongly desired and supported by CEO Pat Gelsinger.