When we talked about the TSMC 2nm chips we focused extensively on the meaning of production node and on the changes that introduce transistor miniaturization techniques based on the use of extreme ultraviolet (EUV) lithography, especially with the new High-NA EUV scanners to make even “denser” chips.
According to what was revealed by Intel’s number one, Pat Gelsinger, the difficulties encountered in the past with the transition to the 10 nm node and the lengthy migration from a construction process to a more advanced one would now be a distant memory. Intel, in fact, opened the angstrom era: until “yesterday” the reference unit of measurement to express the size of the transistors it was the nanometer. With the purpose of improve still them performance and theefficiency of chips, now Intel uses theangstrom, tenth part of a nanometer, and announces that in 2026 it will be ready to create 14 Å (angstrom) processors, equivalent to 1.4 nm. Suffice it to say that the section of a hair is equivalent to 800,000 angstroms, RNA viruses have dimensions between 800 and 1,600 angstroms.
Intel 10 Å (1 nm) chip coming in 2027
In the second half of 2027, Intel even expects to be able to create the first examples of chip a 10 Å (1 nm). The details of the most advanced node are currently unknown but Gelsinger said that, typically, one can expect a performance improvement of 14-15% between one node and the immediately following one. And indeed, in the transition between Intel 7 and Intel 4, the difference was around 15%.
As seen in the graph shared by the company, the company confirms that the adoption of extreme ultraviolet lithography begins with the Intel 4 and Intel 3 nodes, and then culminates with the construction processes that mark the transition to the angstrom unit.
Intel innovations will also focus on the side packaging
The knot Intel 20A sees the integration of two new technologies: the PowerVIA rear power supply and the use of GAA RibbonFET transistors. Intel will also ramp up manufacturing capabilities in terms of packaging advanced for Foveros, EMIB, SIP and HBI:
- Foveros. It is a three-dimensional packaging technology that allows stacking verticale of different chips on a single package, allowing for greater density and performance.
- EMIB (Embedded Multi-die Interconnect Bridge). Packaging technology that allows multiple chips to be connected on a single package through advanced interconnection, optimizing performance and efficiency.
- SIP (Silicon Photonics). It represents the integration of photonic technology in siliconallowing optical data transmission within the chip for better performance.
- HBI (Hybrid Bond Interconnect). It refers to a technology of hybrid interconnection which combines different types of bonds to connect the various components on a package, improving performance and energy efficiency.
Investments in the construction of new factories and in the upgrading of current factories
In addition to existing facilities, the company plans to invest $100 billion over the next five years in factory expansions and investments in new manufacturing sites. Certainly making use of initiatives such as the European Chips Act. Among other things, Germany’s delays in disbursing the budgeted funds could have also brought our country back into contention as one of the first choices for the construction of Intel factories. The company, according to its position statements from January 2024, however, should insist on Germany and Poland.
Intel is therefore working to create fully autonomous factories, which will also make use of robots guided by artificial intelligence. Keevan Esfarjani, executive vice president of Intel, did not indicate when the company will begin using the processor permanently.automation based on IAbut said the latter will have a major impact on every aspect of the company’s business.
The humanoid (?) that Intel is thinking of for its factories is called Cobot AI: This is a collaborative robot that can work together with humans and automate a wide range of production processes.
The images published in the article are taken from the Intel website.