Zen 4c-based AMD EPYC Bergamo processors: how they work

The ever-increasing demand for performance in the field datacenter it has led processor manufacturers to move towards ever more “thrust” designs, capable of combining the need for increasingly dense chips in terms of transistors with the physical limits of Moore’s law. With his AMD EPYC Bergamo, the company led by Lisa Su continues the “tour” of the most beautiful Europen cities. The first processor of the EPYC family presented in 2017 had in fact the code name Naples (Naples). Successors have seen the arrival of Rome, Milan, Genoa and now Bergamo (waiting for Siena e Turin). We remind you that geographical names cannot be the subject of patent rights (registered trademark) therefore not only AMD but also Intel and other companies use them heavily for their respective hardware and software products.

AMD EPYC Bergamo: eat if you present

Officially presented at the event Data Center and AI Technology Premiere As of mid-June 2023, EPYC Bergamo is the first x86 CPU cloud-native based on microarchitecture It was 4c which retains essentially the same feature set as Zen 4 while halving the core size.

The new EPYC Bergamo uses the same SP5 socket as its 96-core EPYC Genoa predecessor but welcomes well 128 core and features a very similar 12-channel DDR5-4800 memory subsystem. The processor uses the same die capable of providing 128 PCIe Gen5 lanes and confirms the other features of the SP5-based offering.

Il design of EPYC Bergamo could not ignore the optimization of energy consumption which guarantees maximum efficiency. AMD has also focused on size of the die and maintaining a low TCO. The TCO (Total Cost of Ownership), represents the cost total incurred over the life of a product, taking into consideration not only the initial purchase price, but also related costs. The Sunnyvale company wanted to invest more in these aspects than in achieving the maxims performance per core.

Made at 5 nm, EPYC Bergamo is in fact a System-on-a-Chip (SoC) for the cloud world which, precisely because of this configuration, represents AMD’s answer to ARM-based datacenter-level SoCs. Think of those of Ampere, Amazon, Google and Microsoft.

AMD’s new EPYC Bergamo offering competes directly with the chips Intel Sierra Forest to 144 cores that mark the debut of E-cores in the line of Xeon CPUs intended for the data center segment. Other opponents are the processors AmpereOne a 192 core.

Zen 4c architecture: what changes compared to Zen 4

At the microarchitecture level, Zen 4c retains the same design as Zen 4. In fact, the first analyzes highlight identical characteristics, also in terms of IPC (instructions per clock). Zen 4c “Dionysus” cores, however, are approximately 35.4% smaller than Zen 4 “Persephone” cores. To achieve this goal, AMD had to implement a number of precautions during the design phase.

EPYC Bergamo is also based on eight core complex die (CCD) which pack 16 Zen 4c cores each, as opposed to the 8 Zen 4 cores per CCD. Each CCD has two Core Complex 8-core with 32MB L3 cache, 16MB for CCX. In contrast, each Zen 4 CCX has 32MB of L2 cache, which tends to be significantly larger than the Zen 4c.

AMD engineers have observed that with Bergamo the area occupied by the core plus L3 cache measures 2.48 mm²35% less than the 3.84 mm² which are found on the standard Zen 4 platform. It is also interesting that AMD currently only uses 8 chiplets Zen 4c with the I/O chiplet at the center, whereas standard EPYC chips use up to twelve Zen 4 chiplets.

It is therefore not excluded that a solution may arrive in the future Zen 4c with 12 chiplets and 192 cores. In this regard, AMD still remains “buttoned up” but the arrival of such a novelty is not excluded.

In short, with Zen 4, the trajectory followed by AMD for the design of EPYC processors changes considerably. With the Bergamo processors, the engineers of the Sunyvale company had to insert 128 Zen 4 class cores in the same “package” with a power between 360W and 400W, such as Genoa. By revising the CCD/CCX structure, lowering the maximum frequencies and using denser SRAM cells, the engineers have brilliantly achieved the goal. We need to check the impact on performance with field tests.

For now, AMD has announced the aforementioned Bergamo processors, theEPYC 9754 con 128 core/256 thread e l’EPYC 9734 with 112 cores/224 threads. The latter has two cores for disabled CCDs.

Dan McNamara, head of AMD’s server division, said that the EPYC Bergamo offer will cause a lot of talk: “because they are cloud-native optimized devices with high density and great performance per watt, excellent in terms of energy efficiency for cloud-native computing“.

The opening image is from AMD.